philips semiconductors product specification trenchmos ? transistor buk9840-55 logic level fet general description quick reference data n-channel enhancement mode logic symbol parameter max. unit level field-effect power transistor in a plastic envelope suitable for surface v ds drain-source voltage 55 v mounting. the device features very i d drain current 10.7 a low on-state resistance and has p tot total power dissipation 1.8 w integral zener diodes giving esd t j junction temperature 150 ?c protection. it is intended for use in r ds(on) drain-source on-state 40 m w automotive and general purpose resistance v gs = 5 v switching applications. pinning - sot223 pin configuration symbol pin description 1 gate 2 drain 3 source 4 drain (tab) limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit v ds drain-source voltage - - 55 v v dgr drain-gate voltage r gs = 20 k w -55v v gs gate-source voltage - - 10 v i d drain current (dc) t sp = 25 ?c - 10.7 a i d drain current (dc) on pcb in fig.19 - 5 a t amb = 25 ?c i d drain current (dc) on pcb in fig.19 - 3.1 a t amb = 100 ?c i dm drain current (pulse peak value) t sp = 25 ?c - 40 a p tot total power dissipation t sp = 25 ?c - 8.3 w p tot total power dissipation on pcb in fig.19 - 1.8 w t amb = 25 ?c t stg , t j storage & operating temperature - - 55 150 ?c esd limiting value symbol parameter conditions min. max. unit v c electrostatic discharge capacitor human body model - 2 kv voltage (100 pf, 1.5 k w ) d g s 4 1 23 january 1998 1 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9840-55 logic level fet thermal resistances symbol parameter conditions typ. max. unit r th j-sp from junction to solder point mounted on any pcb 12 15 k/w r th j-amb from junction to ambient mounted on pcb of fig.18 - 70 k/w static characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit v (br)dss drain-source breakdown v gs = 0 v; i d = 0.25 ma 55 - - v voltage t j = -55?c 50 - - v v gs(to) gate threshold voltage v ds = v gs ; i d = 1 ma 1.0 1.5 2.0 v t j = 150?c 0.6 - - v t j = -55?c - - 2.3 v i dss zero gate voltage drain current v ds = 55 v; v gs = 0 v; - 0.05 10 m a t j = 150?c - - 100 m a i gss gate source leakage current v gs = 5 v - 0.02 1 m a t j = 150?c - - 5 m a v (br)gss gate source breakdown voltage i g = 1 ma 10 - - v r ds(on) drain-source on-state v gs = 5 v; i d = 5 a - 30 40 m w resistance t j = 150?c - - 74 m w dynamic characteristics t mb = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit g fs forward transconductance v ds = 25 v; i d = 5 a; t j = 25?c 11 19 - s c iss input capacitance v gs = 0 v; v ds = 25 v; f = 1 mhz - 1050 1400 pf c oss output capacitance - 205 245 pf c rss feedback capacitance - 110 150 pf t d on turn-on delay time v dd = 30 v; i d = 9 a; - 17 25 ns t r turn-on rise time v gs = 5 v; r g = 10 w ; - 65 100 ns t d off turn-off delay time - 70 105 ns t f turn-off fall time t j = 25?c - 70 105 ns reverse diode limiting values and characteristics t j = -55 to 175?c unless otherwise specified symbol parameter conditions min. typ. max. unit i dr continuous reverse drain t sp = 25?c - - 10.7 a current i drm pulsed reverse drain current t sp = 25?c - - 40 a v sd diode forward voltage i f = 5 a; v gs = 0 v - 0.85 1.1 v t rr reverse recovery time i f = 5 a; -di f /dt = 100 a/ m s; - 45 - ns q rr reverse recovery charge v gs = -10 v; v r = 30 v - .3 - m c january 1998 2 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9840-55 logic level fet avalanche limiting value symbol parameter conditions min. typ. max. unit w dss drain-source non-repetitive i d = 3.6 a; v dd 25 v; - - 60 mj unclamped inductive turn-off v gs = 5 v; r gs = 50 w ; t sp = 25 ?c energy fig.1. normalised power dissipation. pd% = 100 p d /p d 25 ?c = f(t sp ) fig.2. normalised continuous drain current. id% = 100 i d /i d 25 ?c = f(t sp ); conditions: v gs 3 5 v fig.3. safe operating area. t sp = 25 ?c i d & i dm = f(v ds ); i dm single pulse; parameter t p fig.4. transient thermal impedance. z th j-sp = f(t); parameter d = t p /t 0 20 40 60 80 100 120 140 tmb / c pd% normalised power derating 120 110 100 90 80 70 60 50 40 30 20 10 0 bukx840-55 vds/v id/a 1 us 10 us 100 us 1 ms 10 ms 100 ms tp = 0.1 1 10 100 0.1 1 10 55 rds(on) = vds/id dc 0 20 40 60 80 100 120 140 tmb / c id% normalised current derating 120 110 100 90 80 70 60 50 40 30 20 10 0 1e-07 1e-05 1e-03 1e-01 1e+01 t / s zth / (k/w) 1e+02 3e+01 1e+01 3e+00 1e+00 3e-01 1e-01 3e-02 1e-02 0 0.5 0.2 0.1 0.05 0.02 d = t p t p t t p t d buk9840-55 january 1998 3 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9840-55 logic level fet fig.5. typical output characteristics, t j = 25 ?c . i d = f(v ds ); parameter v gs fig.6. typical on-state resistance, t j = 25 ?c . r ds(on) = f(i d ); parameter v gs fig.7. typical transfer characteristics. i d = f(v gs ) ; conditions: v ds = 25 v; parameter t j fig.8. typical transconductance, t j = 25 ?c . g fs = f(i d ); conditions: v ds = 25 v fig.9. normalised drain-source on-state resistance. a = r ds(on) /r ds(on)25 ?c = f(t j ); i d = 5 a; v gs = 5 v fig.10. gate threshold voltage. v gs(to) = f(t j ); conditions: i d = 1 ma; v ds = v gs 0246810 0 5 10 15 20 2.2 2.4 2.6 2.8 3.0 3.2 3.4 4 3.6 10 5 id/a vgs/v = 5 10 15 20 25 1234567891011121314151617181920 gfs/s id/a 0 5 10 15 20 25 20 30 40 50 60 70 80 rds(on)/mohm vgs/v = id/a 5 4 3.6 3.4 3.2 3 buk98xx-55 -100 -50 0 50 100 150 200 0.5 1 1.5 2 2.5 tmb / degc rds(on) normalised to 25degc a 01234 0 5 10 15 20 id/a vgs/v tj/c = 150 25 buk98xx-55 -100 -50 0 50 100 150 200 0 0.5 1 1.5 2 2.5 tj / c vgs(to) / v max. typ. min. january 1998 4 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9840-55 logic level fet fig.11. sub-threshold drain current. i d = f(v gs) ; conditions: t j = 25 ?c; v ds = v gs fig.12. typical capacitances, c iss , c oss , c rss . c = f(v ds ); conditions: v gs = 0 v; f = 1 mhz fig.13. typical turn-on gate-charge characteristics. v gs = f(q g ); conditions: i d = 9 a; parameter v ds fig.14. typical reverse diode current. i f = f(v sds ); conditions: v gs = 0 v; parameter t j fig.15. normalised avalanche energy rating. w dss % = f(t sp ); conditions: i d = 3.6 a fig.16. avalanche energy test circuit. 0 0.5 1 1.5 2 2.5 3 1e-05 1e-05 1e-04 1e-03 1e-02 1e-01 sub-threshold conduction 2% typ 98% 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 5 10 15 20 if/a vsds/v tj/c = 150 25 0.01 0.1 1 10 100 0 0.5 1.0 1.5 2.0 2.5 ciss coss crss vds/v thousands pf 20 40 60 80 100 120 140 tmb / c 120 110 100 90 80 70 60 50 40 30 20 10 0 wdss% 0 5 10 15 20 0 1 2 3 4 5 6 vgs/v qg/nc vds = 14v vds = 44v l t.u.t. vdd rgs r 01 vds -id/100 + - shunt vgs 0 w dss = 0.5 li d 2 bv dss /( bv dss - v dd ) january 1998 5 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9840-55 logic level fet fig.17. switching test circuit. rd t.u.t. vdd rg vds + - vgs 0 january 1998 6 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9840-55 logic level fet printed circuit board dimensions in mm. fig.18. pcb for thermal resistance and power rating for sot223. pcb: fr4 epoxy glass (1.6 mm thick), copper laminate (35 m m thick). 36 60 9 10 4.6 18 4.5 7 15 50 january 1998 7 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9840-55 logic level fet mechanical data fig.19. sot223 surface mounting package. notes 1. this product is supplied in anti-static packaging. the gate-source input must be protected against static discharge during transport or handling. 2. refer to discrete semiconductor packages, data handbook sc18. 3. epoxy meets ul94 v0 at 1/8". unit a 1 b p cd e e 1 h e l p qy w v references outline version european projection issue date iec jedec eiaj mm 0.10 0.01 1.8 1.5 0.80 0.60 b 1 3.1 2.9 0.32 0.22 6.7 6.3 3.7 3.3 2.3 e 4.6 7.3 6.7 1.1 0.7 0.95 0.85 0.1 0.1 0.2 dimensions (mm are the original dimensions) sot223 96-11-11 97-02-28 w m b p d b 1 e 1 e a a 1 l p q detail x h e e v m a a b b c y 0 2 4 mm scale a x 13 2 4 plastic surface mounted package; collector pad for good heat transfer; 4 leads sot223 january 1998 8 rev 1.000
philips semiconductors product specification trenchmos ? transistor buk9840-55 logic level fet definitions data sheet status objective specification this data sheet contains target or goal specifications for product development. preliminary specification this data sheet contains preliminary data; supplementary data may be published later. product specification this data sheet contains final product specifications. limiting values limiting values are given in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of this specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. philips electronics n.v. 1999 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. january 1998 9 rev 1.000
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